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Power-efficient computer technologies

Vol. 47, No. 5/6, 2003

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Rising power consumption in modern computing devices constitutes a mounting barrier to our ability to improve computing capacity and performance. The twelve papers in this double issue describe a broad spectrum of power-efficient computer technologies that span circuits, architecture, power-simulation tools, and system software. Included are two review papers: one on low-power RAM circuits and one on the design of low-power clocking elements.
RD47-5/6
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Please note: Papers are only available in PDF format, while HTML and ASCII versions are under construction.
Table of contents PDF
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Power-efficient computer technologies
Message from the Director, Austin Research Laboratory, IBM Research Division Michael G. Rosenfield
Preface G. N. Elnozahy and R. Joshi, Guest Editors p. 521
Technology and circuits
Review and future prospects of low-voltage RAM circuits Y. Nakagome, M. Horiguchi, T. Kawahara, and K. Itoh p. 525
Ultralow-power SRAM technology R. W. Mann, W. W. Abadeer, M. J. Breitwisch, O. Bula, J. S. Brown, B. C. Colwill, P. E. Cottrell, W. T. Crocco, S. S. Furkay, M. J. Hauser, T. B. Hook, D. Hoyniak, J. M. Johnson, C. M. Lam, R. D. Mih, J. Rivard, A. Moriwaki, E. Phipps, C. S. Putnam, B. A. Rainey, J. J. Toomey, and M. I. Younus p. 553
Clocking and storage elements in a multi-gigahertz environment V. G. Oklobdzija p. 567
Balancing hardware intensity in microprocessor pipelines V. Zyuban and P. N. Strenski p. 585
Fine-grain real-time reconfigurable pipelining S. Kim, C. H. Ziesler, and M. C. Papaefthymiou p. 599
System-on-a-chip
Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits J.-O. Plouchart, N. Zamdmer, J. Kim, M. Sherony, Y. Tan, A. Ray, M. Talbi, L. F. Wagner, K. Wu, N. E. Lustig, S. Narasimha, P. O'Neil, N. Phan, M. Rohn, J. Strom, D. M. Friend, S. V. Kosonocky, D. R. Knebel, S. Kim, K. A. Jenkins, and M. M. Rivier p. 611
The design and application of the PowerPC 405LP energy-efficient system-on-a-chip K. J. Nowka, G. D. Carpenter, and B. C. Brock p. 631
Tools
Design and validation of a performance and power simulator for PowerPC systems H. Shafi, P. J. Bohrer, J. Phelan, C. A. Rusu, and J. L. Peterson p. 641
New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors D. Brooks, P. Bose, V. Srinivasan, M. K. Gschwind, P. G. Emma, and M. G. Rosenfield p. 653
System software
On the performance and use of dense servers W. M. Felter, T. W. Keller, M. D. Kistler, C. Lefurgy, K. Rajamani, R. Rajamony, F. L. Rawson, B. A. Smith, and E. Van Hensbergen p. 671
Maximizing the system value while satisfying time and energy constraints C. A. Rusu, R. Melhem, and D. Mossé p. 689
Workload-based power management for parallel computer systems D. J. Bradley, R. E. Harper, and S. W. Hunter p. 703
Author index for Volume 47 p. 719
Subject index for Volume 47 p. 725
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