Notes on Multi-Processor Architectures

James L. Peterson

March 1998

• Motivation
  • Throughput -- run more jobs at a time
  • Parallel Processing -- run algorithms with parallel steps
    Fine grain, Coarse grain
  • Reliability, Fault Tolerant
  • Number of processors -- 2, 4, 8, 32, 128, 1024

• Processors
  • Tightly coupled -- share memory
  • Loosely coupled -- each with separate memory
  • Intermediate -- shared and local memory

• Interprocessor Communication and connection
  • memory based
  • interrupt based
  • bus or net communication (packets)

• Caches
  • Cache coherency
  • TLB coherency
  • Delayed stores
  • Multi-level caches (L1, L2)
  • Software selected coherency

• Virtual Memory Issues
  • Aliasing
  • Same memory image per processor
  • Address generation (prefix cpu id?)
  • Single or multiple page tables
  • Direct or Inverted Page Tables
  • Read-only vs. Modified page tables (by hardware)
  • Modifying page tables by software
  • Amount of Real memory needed

• Peer to Peer or Master/Slave

• Symmetric or Asymmetric
  • Load cpu id

• I/O
  • who gets interrupts (interrupt distribution)
  • memory consistency during I/O
  • channels or special processors
  • symmetric or asymmetric I/O
  • Are all interrupt vectors the same for all cpus

• Clocks
  • Is there a shared clock or timer?
  • If separate clocks, are they coherent?
  • clock synchronization

• Locking on updates
  • special instructions
  • test and set
  • compare and swap
  • spin locks
  • wait locks
  • interrupt based

• IPL, booting questions
  • All boot or special one boots

• Tolerance of MP
  • code does not break in move from UP to MP

• Exploitation of MP
  • code makes use of existance of MP (requires new support)

• Hardware changes
  • increased performance with same architecture (multiple ALUs)

• Kernel changes
  • increased system capability (cpu scheduling of processes)
  • SVC mechanism

• User Level changes
  • mp using fork for user level
  • additional system calls (threads, RPC, messages, ...)
  • non-standard interface
  • compiler, library support

• Testing, debugging

• Reliability, Robustness

• System Performance and Balance
  • Memory Contention
  • Cache invalidation